Title
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging
Abstract
In this paper we propose1 a new method for the design of duplex fault-tolerant systems with early error detection and high availability. All the scannable memory elements (Flip-Flops) of the duplicated system are implemented as multi-mode memory elements according to [9] allowing during normal operation to accumulate a signature of its states in its scan-paths. By continously comparing a 1-bit sequence of the compacted scan-out outputs of the accumulated signatures of the duplicated systems an error can be already detected and a recovery procedure started before an erroneous result appears at the system outputs when a computations is completed. The accumulation of a signature during normal operation can also be used for debugging at-speed. For this application the system need not be duplicated.
Year
DOI
Venue
2001
10.1109/VTS.2001.923437
VTS
Keywords
Field
DocType
early error detection,compacted scan-out output,multi-mode memory element,system output,at-speed debugging,duplex fault-tolerant system,normal operation,1-bit sequence,erroneous result,scannable memory element,high availability,fault tolerance,fault tolerant system,hardware,vlsi,system testing,fault tolerant,debugging,error detection,normal operator,fault detection,system on chip,redundancy
System testing,Fault detection and isolation,Computer science,Real-time computing,Electronic engineering,Error detection and correction,Redundancy (engineering),Fault tolerance,High availability,Debugging,Recovery procedure
Conference
ISSN
Citations 
PageRank 
1093-0167
2
0.39
References 
Authors
1
5
Name
Order
Citations
PageRank
E. S. Sogomonyan1878.03
A. Morosov2304.11
J. Rzeha330.76
Michael Gössel427142.58
A. Singh5428.59