Name
Abstract | ||
|---|---|---|
A logic optimization criterion for lookup-table based field programmable gate arrays (FPGAs) is presented. Based on this criterion, several key operations of logic optimization, such as extraction, decomposition, resubstitution and simplification, are discussed, so as to make them evaluate the circuit cost in accordance with the target technology. Using our approaches to do logic optimization for lookup-table based FPGAs, we obtain a good starting point for technology mapping. On the basis of 25 benchmark examples, our optimized circuits require 14% fewer configurable logic blocks (CLBs) than the circuits optimized by MIS-II if both are subsequently mapped using MIS-pga. Moreover, the number of circuit levels is also slightly improved |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/ICCD.1994.331847 | ICCD |
Keywords | Field | DocType |
optimisation,benchmarks,lookup table based fpga,circuit cost evaluation,technology mapping,logic arrays,resubstitution,architecture oriented logic optimization,simplification,lookup table,circuit levels,logic design,decomposition,mis-ii,computer architecture,field programmable gate arrays,configurable logic blocks,table lookup,extraction,mis-pga,logic circuits,field programmable gate array,boolean functions,algorithm design and analysis,cmos technology,cost function | Logic synthesis,Logic gate,Complex programmable logic device,Sequential logic,Pass transistor logic,Logic optimization,Computer science,Parallel computing,Programmable logic array,Logic family | Conference |
ISSN | Citations | PageRank |
1063-6404 | 1 | 0.40 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Aiguo Lu | 1 | 739 | 224.20 |
| Jonathan Saul | 2 | 1 | 0.40 |
| Erik L Dagless | 3 | 26 | 7.29 |