Name
Abstract | ||
|---|---|---|
A 12b 50 MS/s 0.18 μ m CMOS pipeline ADC is described. The proposed capacitor and operational amplifier (op-amp) sharing techniques merge the front-end sample-and-hold amplifier (SHA) and the first multiplying digital-to-analog converter (MDAC1) to achieve low power without an additional reset timing and a memory effect. The second and third MDACs share a single op-amp to reduce power consumption ... |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/TCSI.2011.2112591 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Capacitors,Clocks,Pipelines,Power demand,Capacitance,Timing,Bandwidth | Capacitor,Dynamic range,Capacitance,CMOS,Electronic engineering,Bandwidth (signal processing),Electrical engineering,Operational amplifier,Mathematics,Least significant bit,Amplifier | Journal |
Volume | Issue | ISSN |
58 | 9 | 1549-8328 |
Citations | PageRank | References |
13 | 0.97 | 18 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyung-Hoon Lee | 1 | 71 | 15.77 |
| Kwangsoo Kim | 2 | 652 | 62.13 |
| Seunghoon Lee | 3 | 244 | 61.57 |