Title
A Symmetric Odd-Even Routing Model in Network-on-Chip
Abstract
The performance of adaptive routing strongly depends on its degree of adaptive ness in Network-on-chip (NoC). It is observed that there exists adaptive imbalance between even and odd columns in the well-known odd-even (OE) model. In this paper, we present an improved OE model, called symmetric OE model (SOE), which provides higher level of adaptive ness and uses central deadlock buffers to avoid deadlock. Simulation results show that the proposed SOE routing model distributes traffic more uniformly and achieves performance improvement in terms of network saturation throughput and package latency by 18 and 25 percent respectively on average comparing with the previous work of OE.
Year
DOI
Venue
2012
10.1109/ICIS.2012.20
ACIS-ICIS
Keywords
Field
DocType
symmetric oe model,higher level,central deadlock buffer,network routing,adaptive ness,symmetric odd-even routing model,odd-even routing,network saturation throughput,proposed soe routing model,central deadlock buffers,performance improvement,deadlock,soe routing model,adaptive routing performance,adaptive routing,traffic distribution,adaptiveness,buffer circuits,improved oe model,performance evaluation,adaptive imbalance,package latency,noc,network-on-chip,algorithm design and analysis,simulation,algorithm design,throughput,network on chip,routing
Topology,Algorithm design,Latency (engineering),Computer science,Deadlock,Computer network,Network on a chip,Saturation throughput,Throughput,Adaptive routing,Performance improvement
Conference
ISBN
Citations 
PageRank 
978-1-4673-1536-4
5
0.47
References 
Authors
12
2
Name
Order
Citations
PageRank
Su Hu161.51
Xiaola Lin2109978.09