Name
Abstract | ||
|---|---|---|
A DMA controller that operates in the cycle-stealing mode transfers data by "stealing" bus cycles from an executing program. This cycle stealing operation retards the progress of the executing program and extends its execution time. We first present a method that bounds the worst-case execution time of a program executing concurrently with a cycle-stealing DMA I/O operation in the simple case where the execution time of each machine instruction is fixed. We next extend this method to deal with the case of instruction-cache architectures. We demonstrate the effectiveness of our methods by the results of simulations of several programs. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/REAL.1996.563724 | RTSS |
Keywords | Field | DocType |
o interference,dma controller,machine instruction,execution time,program execution time,cycle-stealing dma,o operation,instruction-cache architecture,bus cycle,worst-case execution time,simple case,cycle-stealing mode transfers data,data transfer,concurrent computing,integer linear programming,computational complexity,pipelines,real time systems,computer architecture,upper bound,instruction sets,computational modeling,computer science,worst case execution time,interference | Cycle stealing,Control theory,Worst-case execution time,Data transmission,Instruction set,Computer science,Parallel computing,Real-time computing,Input/output,Operating system,Bounding overwatch,Computational complexity theory | Conference |
ISSN | ISBN | Citations |
1052-8725 | 0-8186-7689-2 | 8 |
PageRank | References | Authors |
0.82 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yi Huang | 1 | 850 | 98.48 |
| J. W.-S. Liu | 2 | 451 | 34.30 |
| D. Hull | 3 | 8 | 0.82 |