Name
Abstract | ||
|---|---|---|
Due to increasing cache-miss latencies, cache control instructions are being implemented for future systems. The authors study the memory referencing behavior of individual machine-level instructions using simulations of fully-associative caches under MIN replacement. Their objective is to obtain a deeper understanding of useful program behavior that can be eventually employed at optimizing programs and to motivate architectural features aimed at improving the efficacy of memory hierarchies. The simulation results show that a very small number of load/store instructions account for a majority of data cache misses. Specifically, fewer than 10 instructions account for half the misses for six out of nine SPEC89 benchmarks. Selectively prefetching data referenced by a small number of instructions identified through profiling can reduce overall miss ratio significantly while only incurring a small number of unnecessary prefetches |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/MICRO.1993.282748 | MICRO |
Keywords | Field | DocType |
store instruction latency,scheduling,clusters,vliw,profiling,dynamic scheduling,degradation,registers,threads | Small number,Predictability,Dataflow architecture,Scheduling (computing),Computer science,Cache,Profiling (computer programming),Parallel computing,Real-time computing,Thread (computing),Memory architecture | Conference |
ISBN | Citations | PageRank |
0-8186-5280-2 | 48 | 6.64 |
References | Authors | |
12 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Santosh G. Abraham | 1 | 762 | 124.08 |
| Rabin A. Sugumar | 2 | 211 | 68.51 |
| Daniel Windheiser | 3 | 129 | 24.82 |
| B. Ramakrishna Rau | 4 | 1290 | 183.17 |
| rajiv gupta | 5 | 4301 | 364.53 |