Name
Abstract | ||
|---|---|---|
In many embedded systems for video surveillance distinctive features are used for the detection of objects. In this contribution a real-time FPGA implementation of a feature detector, namely the SUSAN algorithm is described. As the original SUSAN algorithm performs poorly on non-synthetic images a significant quality improvement of this algorithm is presented. The hardware accelerator outperforms a comparable software version running on an Intel Core2Duo E8400 core at 3.00GHz and delivers almost the same execution time compared to an implementation of the Harris corner detector running on an Nvidia GeForce 8800 GTX GPU. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/FPL.2009.5272524 | International Conference on Field Programmable and Logic Applications |
Keywords | Field | DocType |
edge detection,corner detection,mathematical model,software version,feature detector,quality improvement,real time,feature extraction,field programmable gate arrays,brightness,embedded systems,pixel,embedded system,hardware,harris corner detector,hardware accelerator | Object detection,Corner detection,Computer science,Edge detection,Algorithm,Field-programmable gate array,Feature extraction,Pixel,Hardware acceleration,Computer hardware,Software versioning | Conference |
ISSN | Citations | PageRank |
1946-1488 | 12 | 0.94 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christopher Claus | 1 | 221 | 20.39 |
| Robert Huitl | 2 | 142 | 8.35 |
| Joachim Rausch | 3 | 12 | 0.94 |
| Walter Stechele | 4 | 365 | 52.77 |