Name
Title | ||
|---|---|---|
Reconfiguration Process Optimization Of Dynamically Coarse Grain Reconfigurable Architecture For Multimedia Applications |
Abstract | ||
|---|---|---|
This paper presents a novel architecture design to optimize the reconfiguration process of a coarse-grained reconfigurable architecture (CGRA) called Reconfigurable Multimedia System II (REMUS-II). In REMUS-II, the tasks in multi-media applications are divided into two parts: computing-intensive tasks and control-intensive tasks. Two Reconfigurable Processor Units (RPUs) for accelerating computing-intensive tasks and a Micro-Processor Unit (mu PU) for accelerating control-intensive tasks are contained in REMUS-II. As a large-scale CGRA. REMUS-II can provide satisfying solutions in terms of both efficiency and flexibility. This feature makes REMUS-II well-suited for video processing, where higher flexibility requirements are posed and a lot of computation tasks are involved. To meet the high requirement of the dynamic reconfiguration performance for multimedia applications, the reconfiguration architecture of REMUS-II should be well designed. To optimize the reconfiguration architecture of REMUS-II, a hierarchical configuration storage structure and a 3-stage reconfiguration processing structure are proposed. Furthermore, several optimization methods for configuration reusing are also introduced, to further improve the performance of reconfiguration process. The optimization methods include two aspects: the multi-target reconfiguration method and the configuration caching strategies. Experimental results showed that, with the reconfiguration architecture proposed, the performance of reconfiguration process will be improved by 4 times. Based on RTL simulation, REMUS-II can support the 1080p@32 fps of H.264 HiP@Level4 and 1080p@40 fps High-level MPEG-2 stream decoding at the clock frequency of 200 MHz. The proposed REMUS-II system has been implemented on a TSMC 65 nm process. The die size is 23.7 mm(2) and the estimated on-chip dynamic power is 620 mW. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1587/transinf.E95.D.1858 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
REMUS-II, coarse grain reconfigurable architecture, reconfiguration process, multimedia application | Architecture,Computer science,Control reconfiguration,Embedded system,Process optimization | Journal |
Volume | Issue | ISSN |
E95D | 7 | 1745-1361 |
Citations | PageRank | References |
5 | 0.49 | 10 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bo Liu | 1 | 10 | 4.67 |
| peng cao | 2 | 33 | 4.96 |
| Min Zhu | 3 | 5 | 0.49 |
| Jun Yang | 4 | 147 | 36.54 |
| leibo liu | 5 | 816 | 116.95 |
| Shaojun Wei | 6 | 555 | 102.32 |
| Longxing Shi | 7 | 116 | 39.08 |