Name
Abstract | ||
|---|---|---|
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent of multiprocessor systems-on-chips (SoCs) makes it even more challenging for programmers to utilize the full potential of the computation resources on the chips. In the mean time, the complexity of the chip design creates new reliability challenges. As a result, chip designers and users cannot fully exploit the tremendous silicon resources on the chip. This research proposes a prototype which is composed of a fault-tolerant multiprocessor SoC and a coupled single program, multiple data (SPMD) programming framework. We use a SystemC based modeling and simulation environment to design and analyze this prototype. Our analysis shows that this prototype as a reliable computing platform constructed from the potentially unreliable chip resources, thus protecting the previous investment of hardware and software designs. Moreover, the promising application-driven simulation results shed light on the potential of a scalable and reliable multiprocessing computing platform for a wide range of mission-critical applications |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/DAC.2006.229177 | DAC |
Keywords | Field | DocType |
fault-tolerant multiprocessor soc,systemc,reliable computing platform,integrated circuit testing,simulation environment,multiprocessor system,multiprocessor system-on-chips,integrated circuit modelling,run-time verification,reliable multiprocessing computing platform,programming framework,full potential,promising application-driven simulation result,unreliable chip resource,verification,high performance ics,multiprocessing computing platform,system-on-chip,multiprocessing systems,logic design,integrated circuit design,run-time fault recovery,design,experimentation,retargetable simulation,chip designer,fault-tolerance,fault-tolerant multiprocessor,network-on-chip,software design,chip design,performance,multiprocessing,integrated circuit,system on chip,fault tolerance,chip,fault tolerant,modeling and simulation,fault tolerant system,network on chip | Computer architecture,System on a chip,Computer science,Network on a chip,Real-time computing,SystemC,Chip,Multiprocessing,Fault tolerance,Integrated circuit design,Software framework,Embedded system | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-59593-381-6 | 8 |
PageRank | References | Authors |
0.47 | 6 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xinping Zhu | 1 | 526 | 38.36 |
| Wei Qin | 2 | 131 | 10.24 |