Paper Info
Title
Automated design flow for no-cost configuration error detection in sram-based FPGAs.
Abstract
Soft errors in the configuration memory of SRAM-based FPGAs cause significant and remanent application disturbances. However, classical mitigation techniques based on massive redundancy are too costly for most applications. The method presented in this paper is based on selective redundancy in partially used LUTs. It can be applied so that no hardware is added at the system level and it has been automated in standard design flows for Xilinx and Altera families. The detection of soft errors in the configuration is performed within one clock period. Experimental results on benchmark implementations are discussed, showing the good ratio between coverage and block-level overheads, with almost no impact on power and delay. The differences between applying the approach to Virtex V and Stratix IV devices are also discussed.
Year
DOI
Venue
2013
10.1109/ReConFig.2013.6732272
ReConFig
Keywords
Field
DocType
logic design,field programmable gate arrays
Logic synthesis,Stratix,Computer science,Parallel computing,Field-programmable gate array,Error detection and correction,Design flow,Real-time computing,Static random-access memory,Redundancy (engineering),Virtex,Embedded system
Conference
ISSN
ISBN
Citations 
2325-6532
978-1-4799-2078-5
1
PageRank 
References 
Authors
0.39
8
2
Name
Order
Citations
PageRank
Mohamed Ben Jrad161.93
Régis Leveugle235444.83