Name
Abstract | ||
|---|---|---|
The enormous state spaces which must be searched when verifying the correctness of, or generating tests for, complex circuits precludes the use of traditional approaches. Hard-to-find abstractions are often required to simplify the circuits and make the problems tractable. This paper presents a simple and automatic method to extract the control flow of a circuit so that the resulting state space can be explored for validation coverage analysis and automatic test generation. This control flow, capturing the essential “behavior” of the circuit, is represented as a finite state machine called the ECFM (Extracted Control Flow Machine). Simulation is currently the primary means of verifying large circuits, but the definition of a coverage measure for simulation vectors is an open problem. We define functional coverage as the amount of control behavior covered by the test suite. We then combine formal verification techniques, using BDDs as the underlying representation, with traditional ATPG techniques to automatically generate additional sequences which traverse uncovered parts of the control state graph. We also demonstrate how the same abstraction techniques can complement ATPG techniques when attacking hard-to-detect faults in the control part of the design for which conventional ATPG alone proves to be inadequate or inefficient at best. Results on large designs show significant improvement over conventional algorithms |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/12.656068 | IEEE Trans. Computers |
Keywords | Field | DocType |
resulting state space,control state graph,abstraction techniques,control part,finite state machine,conventional atpg,control flow,control behavior,enormous state space,atpg technique,test generation,validation coverage analysis,coverage measure,space exploration,state space,formal verification,automata,automatic test pattern generation,automatic control | Test suite,Automatic test pattern generation,Computer science,Parallel computing,Control flow,Correctness,Finite-state machine,Theoretical computer science,Real-time computing,State space,Traverse,Formal verification | Journal |
Volume | Issue | ISSN |
47 | 1 | 0018-9340 |
Citations | PageRank | References |
62 | 3.62 | 16 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dinos Moundanos | 1 | 128 | 12.90 |
| J. Abraham | 2 | 4905 | 608.16 |
| Yatin Hoskote | 3 | 1234 | 85.97 |