Name
Abstract | ||
|---|---|---|
The continuation of Moore's law by conventional CMOS scaling is becoming challenging. 3D Packaging with 3D through silicon vias (TSV) interconnects is showing promise for extending scaling using mature silicon technology, providing another path towards the "More than Moore". Two years ago, the big unceasing question was "Why 3D?" Today, as we move forward with the concrete implementation of the technology, the questions are now "When 3D?" and "How 3D?" There are quite a few brave souls who have taken this disruptive interconnect technology and are investing in it today to gain benefit from it. However, for many the lingering questions remain "Are we there yet?" "Is it now or the future?" |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1837274.1837350 | DAC |
Keywords | Field | DocType |
conventional cmos scaling,brave soul,integrated circuits,3-d,silicon vias,big unceasing question,mature silicon technology,concrete implementation,cmos integrated circuits,moore s law,packaging,stacking,cmos technology,integrated circuit,design methodology,integrated circuit packaging,through silicon via,silicon | Electronic engineering,Cmos scaling,Engineering,Interconnect technology,Moore's law | Conference |
ISSN | ISBN | Citations |
0738-100X | 978-1-4244-6677-1 | 1 |
PageRank | References | Authors |
0.34 | 1 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Samta Bansal | 1 | 1 | 0.34 |
| Juan C. Rey | 2 | 3 | 1.62 |
| Andrew Yang | 3 | 10 | 3.74 |
| Myung-Soo Jang | 4 | 3 | 0.77 |
| LC Lu | 5 | 1 | 0.34 |
| Philippe Magarshack | 6 | 111 | 14.88 |
| Pol Marchal | 7 | 78 | 8.43 |
| Riko Radojcic | 8 | 31 | 4.68 |