Name
Abstract | ||
|---|---|---|
A high-performance 1D-DCT architecture is proposed. It is based on the New Distributed Arithmetic Architecture algorithm (NEDA) [1]. Enhancements to NEDA are proposed to reduce the number of computations. Only addition operations are used, with 42 additions to compute the outputs for an 8x1 DCT. No subtractions, multiplications, or ROM is needed. High-throughput is achieved by pipelining the architecture. In every clock cycle, it receives eight pixels (each is 9-bits) as inputs, and produces eight DCT coefficients (each is 14-bits). The delay of one pipeline stage is the delay of a 3-level 4:2 compressor tree. The architecture is implemented in 0.35µ technologies; it runs at 1.5 GHz, and processes 108 Gbps of image/video sequence data. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ASAP.2000.862387 | ASAP |
Keywords | Field | DocType |
dsp chip,videoconference,frequency domain analysis,parallel algorithms,computer architecture,high throughput,transform coding,vlsi,video compression,data compression | Pipeline (computing),Digital signal processor,Computer science,Parallel algorithm,Discrete cosine transform,Parallel computing,Transform coding,Data compression,Cycles per instruction,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
1063-6862 | 0-7695-0716-6 | 3 |
PageRank | References | Authors |
0.65 | 4 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ahmed M. Shams | 1 | 96 | 10.75 |
| Magdy A. Bayoumi | 2 | 803 | 122.04 |