Name
Abstract | ||
|---|---|---|
In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate, and are naturally applicable to various actual devices for simulating power analysis. Furthermore, we demonstrate the weakness of previously known hardware countermeasures for both our model and FPGA and suggest secure conditions for the hardware countermeasure. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1093/ietfec/e90-a.1.169 | IEICE Transactions |
Keywords | Field | DocType |
logic level,dpa countermeasures,new model,cmos circuit,various actual device,dpa leakage,leakage analysis,simulating power analysis,hardware countermeasure,secure condition,logic information,hardware countermeasures,transition probability,side channel attacks,differential power analysis | Countermeasure,Power analysis,Leakage (electronics),Field-programmable gate array,CMOS,Logic level,Side channel attack,Electronic circuit,Mathematics,Embedded system | Journal |
Volume | Issue | ISSN |
E90-A | 1 | 0916-8508 |
Citations | PageRank | References |
3 | 0.43 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Minoru Saeki | 1 | 243 | 14.88 |
| Daisuke Suzuki | 2 | 306 | 21.80 |
| Tetsuya Ichikawa | 3 | 346 | 30.90 |