Name
Abstract | ||
|---|---|---|
The optimum bit/stage configuration is an important issue in the design of a low-power pipeline analog-to-digital converter ( ADC). Prior to this work, power considerations based on a linear-model have been reported [ 1]. In this letter, the slew-rate limitation, a non-linear effect, is taken into consideration in low-power design. In the case of a 10-bit, 200-MSPS ADC using 90-nm CMOS technology, the lowest power bit-arrangement was found to be 1.5 bit/stage. A test chip was fabricated for confirmation, and a power dissipation of 105 mW was achieved. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1587/elex.2.429 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
analog-to-digital converter, ADC, low-power design | SINADR,Boost converter,Computer science,Flyback converter,Forward converter,Ćuk converter,Electronic engineering,Successive approximation ADC,Buck converter,Integrating ADC | Journal |
Volume | Issue | ISSN |
2 | 15 | 1349-2543 |
Citations | PageRank | References |
1 | 0.50 | 3 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomohiko Ito | 1 | 16 | 4.40 |
| Takeshi Ueno | 2 | 20 | 4.27 |
| Daisuke Kurose | 3 | 17 | 5.11 |
| Takafumi Yamaji | 4 | 55 | 18.00 |
| Tetsuro Itakura | 5 | 187 | 33.44 |