Name
Abstract | ||
|---|---|---|
Caches play a major role in the performance of high-speed computer systems. Trace-driven simulator is the most widely used method to evaluate cache architectures. However, as the cache design moves to more complicated architectures, along with the size of the trace is becoming larger and larger. Traditional simulation methods are no longer practical due to their long simulation cycles. Several techniques have been proposed to reduce the simulation time of sequential trace-driven simulation. This paper considers the use of generic GPU to accelerate cache simulation which exploits set-partitioning as the main source of parallelism. We develop more efficient parallel simulation techniques by introducing more knowledge into the Compute Unified Device Architecture (CUDA) on the GPU. Our experimental result shows that the new algorithm gains 2.76x performance improvement compared to traditional CPU-based sequential algorithm. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISPA.2009.51 | ISPA |
Keywords | Field | DocType |
parallel algorithms,algorithm design and analysis,solid modeling,computer architecture,coprocessors,computational modeling,data models,acceleration,cache architecture,algorithms,gpgpu | Cache-oblivious algorithm,Computer science,Cache,Parallel algorithm,Parallel computing,Cache-only memory architecture,Cache algorithms,Cache coloring,General-purpose computing on graphics processing units,Sequential algorithm | Conference |
Volume | Issue | ISSN |
null | null | null |
ISBN | Citations | PageRank |
978-0-7695-3747-4 | 7 | 0.58 |
References | Authors | |
11 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Han Wan | 1 | 28 | 10.98 |
| Xiaopeng Gao | 2 | 55 | 10.43 |
| Zhiqiang Wang | 3 | 158 | 35.98 |
| Yi Li | 4 | 22 | 1.16 |