Name
Abstract | ||
|---|---|---|
Packet-switched NoCs are efficient communication architectures for future MP-SoC platforms. However the run-time management of their communication, especially congestion avoidance is a challenging task. This paper discusses a distributed HW/SW congestion control technique. Hard- ware modules detect early signs of congestion and traffic is re-shaped accordingly to reduce conges- tion. The shape of the traffic is computed with binomial algorithms running on simple distributed microcontrollers. The hardware and software extensions we propose to our system provide a congestion control solution that proves to be low-latency (100 clock cycles) and has a low area contribution to the router hardware (about 5% in UMC 0.13 technology). |
Year | Venue | Keywords |
|---|---|---|
2005 | PARCO | congestion control,low latency,time management,network on chip |
Field | DocType | Citations |
Computer science,Transmission delay,Packet loss,Computer network,Flow control (data),Network congestion,TCP tuning,Switched communication network,Network traffic control,Explicit Congestion Notification | Conference | 11 |
PageRank | References | Authors |
0.58 | 6 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Théodore Marescaux | 1 | 225 | 20.77 |
| A. Rangevall | 2 | 11 | 0.58 |
| Vincent Nollet | 3 | 148 | 9.06 |
| Andrei Bartic | 4 | 165 | 16.81 |
| Henk Corporaal | 5 | 1787 | 166.20 |