Paper Info
Title
Test scheme for switched-capacitor circuits by digital analyses
Abstract
This paper proposes a test scheme for measuring the ratio of a pair of capacitors of switched-capacitor (SC) circuits under test (CUT). A specific test signal called step-ramp signal (SRS) is designed. It accurately corresponds to a reference counter. With multiple gains design, a preamplifier following the CUT makes the output of the CUT larger to ensure that the output of the preamplifier is larger than that of the sampled voltage of the SRS inputted to the CUT. The difference between the output of the preamplifier and sampled voltage of the SRS is matched to a set of reference counter output codes. The ratio extracting from the codes can be simply and accurately calculated with digital circuits. This method is suitable to be implemented with Built-In Self-Test (BIST) structure for features on low chip area overhead and short test time. The demonstration is done by Ispice simulation. The accuracy of all ramp pieces of the SRS are within 0.036% and the method gives high accuracy of ratio measurement.
Year
DOI
Venue
2009
10.1109/DDECS.2009.5012113
DDECS
Keywords
Field
DocType
ispice simulation,ratio measurement,switched-capacitor circuit,reference counter,test scheme,specific test signal,built-in self-test,short test time,digital analysis,step-ramp signal,reference counter output code,high accuracy,accuracy,chip,digital filters,voltage,circuit analysis,gain,mixed signal circuits,radiation detectors,design for testability,switched capacitor circuits,switched capacitor filter,capacitors,digital circuits,preamplifiers,switched capacitor,preamplifier,circuit switched
Digital electronics,Preamplifier,Capacitor,Digital filter,Computer science,Chip,Switched capacitor,Electronic engineering,Mixed-signal integrated circuit,Built-in self-test
Conference
ISSN
Citations 
PageRank 
2334-3133
1
0.37
References 
Authors
2
1
Name
Order
Citations
PageRank
Yun-Che Wen1293.52