Name
Abstract | ||
|---|---|---|
In this paper, we propose a pseudo dynamic buffer (PDB) for footed domino logic circuit implementation. Using the proposed PDB structure, the output pulse during the precharge process is prevented from propagating to the output stage, as is the case in conventional case. As a result, up to half of the power is saved compared to a conventional domino gate, while improving the sampling window of the dynamic gate. This PDB structure is applicable not only for Pull-down network (N-type) dynamic logic, but also for Pull-up networks (P-type). Simulation results illustrate improved performance using the proposed scheme compared to the conventional dynamic logic for different loading conditions, clock frequencies and logic functions. In addition, our proposed design reduces the clock loading from conventional three to two transistors. As a result, the proposed scheme significantly saves power due to lower load capacitance on the clock bus. Test structures are fabricated in 0.35@mm CMOS technology. Measurement results validate the proposed concept and illustrate power saving as compared to conventional design. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1016/j.vlsi.2011.08.003 | Integration |
Keywords | Field | DocType |
low power,dynamic logic,proposed concept,dynamic gate,dynamic logic circuit design,pseudo dynamic buffer,conventional dynamic logic,proposed pdb structure,conventional domino gate,proposed scheme,conventional case,conventional design,proposed design | Domino logic,Sequential logic,Pass transistor logic,Computer science,Logic optimization,Circuit design,Electronic engineering,Real-time computing,Dynamic logic (digital electronics),Asynchronous circuit,AND gate | Journal |
Volume | Issue | ISSN |
45 | 4 | 0167-9260 |
Citations | PageRank | References |
1 | 0.37 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fang Tang | 1 | 1 | 0.37 |
| Amine Bermak | 2 | 493 | 90.25 |
| Zhouye Gu | 3 | 70 | 7.62 |