Name
Title | ||
|---|---|---|
Highly scalable on-the-fly interleaved address generation for UMTS/HSPA+ parallel turbo decoder |
Abstract | ||
|---|---|---|
High throughput parallel interleaver design is a major challenge in designing parallel turbo decoders that conform to high data rate requirements of advanced standards such as HSPA+. The hardware complexity of the HSPA+ interleaver makes it difficult to scale to high degrees of parallelism. We propose a novel algorithm and architecture for on-the-fly parallel interleaved address generation in UMTS/HSPA+ standard that is highly scalable. Our proposed algorithm generates an interleaved memory address from an original input address without building the complete interleaving pattern or storing it; the generated interleaved address can be used directly for interleaved writing to memory blocks. We use an extended Euclidean algorithm for modular multiplicative inversion as a step towards reversed intra-row permutations in UMTS/HSPA+ standard. As a result, we can determine interleaved addresses from original addresses. We also propose an efficient and scalable hardware architecture for our method. Our design generates 32 interleaved addresses in one cycle and satisfies the data rate requirement of 672 Mbps in HSPA+ while the silicon area and frequency is improved compared to recent related works. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ASAP.2013.6567601 | ASAP |
Keywords | Field | DocType |
parallel turbo decoder,interleaved writing,high degree,high throughput parallel interleaver,extended euclidean algorithm,original input address,interleaved memory address,scalable on-the-fly interleaved address,original address,on-the-fly parallel interleaved address,interleaved address,high data rate requirement,algorithm design and analysis,codecs,computer architecture,decoding,writing,indexes,turbo codes,umts | Interleaved memory,Algorithm design,UMTS frequency bands,Computer science,Turbo code,Extended Euclidean algorithm,Real-time computing,Interleaving,Scalability,Hardware architecture | Conference |
Citations | PageRank | References |
2 | 0.42 | 7 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Aida Vosoughi | 1 | 109 | 8.51 |
| Joseph R. Cavallaro | 2 | 1175 | 115.35 |
| Guohui Wang | 3 | 1088 | 60.78 |
| Hao Shen | 4 | 224 | 32.93 |
| Yuanbin Guo | 5 | 67 | 9.22 |