Title
Overcoming post-silicon validation challenges through quick error detection (QED)
Abstract
Existing post-silicon validation techniques are generally ad hoc, and their cost and complexity are rising faster than design cost. Hence, systematic approaches to post-silicon validation are essential. Our research indicates that many of the bottlenecks of existing post-silicon validation approaches are direct consequences of very long error detection latencies. Error detection latency is the time elapsed between the activation of a bug during post-silicon validation and its detection or manifestation as a system failure. In our earlier papers, we created the Quick Error Detection (QED) technique to overcome this significant challenge. QED systematically creates a wide variety of post-silicon validation tests to detect bugs in processor cores and uncore components of multi-core System-on-Chips (SoCs) very quickly, i.e., with very short error detection latencies. In this paper, we present an overview of QED and summarize key results: 1. Error detection latencies of "typical" post-silicon validation tests can range up to billions of clock cycles. 2. QED shortens error detection latencies by up to 6 orders of magnitude. 3. QED enables 2- to 4-fold improvement in bug coverage. QED does not require any hardware modification. Hence, it is readily applicable to existing designs.
Year
DOI
Venue
2013
10.7873/DATE.2013.077
DATE
Keywords
Field
DocType
debug,silicon,hardware,computer bugs,benchmark testing,post silicon validation,testing,multicore processing,system on chip,verification
Post-silicon validation,Computer science,Parallel computing,Uncore,Real-time computing,Error detection and correction,Multi-core processor,Debugging,Embedded system,Error detection latency
Conference
ISSN
Citations 
PageRank 
1530-1591
3
0.38
References 
Authors
41
7
Name
Order
Citations
PageRank
David Lin124314.80
Ted Hong22098.52
Yanjing Li339120.34
Farzan Fallah455743.73
Donald S. Gardner524536.33
Nagib Hakim6251.90
Subhasish Mitra73657228.90