Name
Abstract | ||
|---|---|---|
We describe a system HIDE, that automatically creates VHDL bus-interface models from timhtg and bus-state diagrams. HIDE shrhtks model generation time to days from months. An Intel iAPX80386 model was developed in less than one week. HIDE can also be used to develop executable specifications, as its inputs are a nmnal element of the IC design process. |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/DAC.1992.227808 | DAC |
Keywords | Field | DocType |
computer science,vhdl,state diagram,very large scale integration,automatic control,formal verification,design process,process design,automation,documentation,writing | Programming language,Computer science,Automatic control,Real-time computing,Automation,Integrated circuit design,Process design,VHDL,Very-large-scale integration,Executable,Embedded system,Formal verification | Conference |
ISSN | ISBN | Citations |
0738-100X | 0-89791-516-X | 1 |
PageRank | References | Authors |
0.46 | 1 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yew-Hong Leong | 1 | 1 | 0.46 |
| William P. Birmingham | 2 | 640 | 97.00 |