Name
Abstract | ||
|---|---|---|
We propose an un-excitability prover for Single Event Upset (SEU) faults affecting the configuration memory of logic resources of SRAM-FPGA systems. In particular, we focus on the subset of untestable faults that cannot even be excited, with the aim of optimizing the generation of test patterns, in particular for in-service testing. SEUs in configuration bits of the logic resources actually used by the system are addressed. This makes our fault model much more accurate than the classical stuck-at fault model. The tool relies on the SAL specification language for the modeling of netlists, and on the SAL model checker for the proof of the un-excitability of faults. Results from the application of the tool to some circuits from the ISCAS and ITC benchmarks are reported. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/IOLTS.2012.6313836 | IOLTS |
Keywords | DocType | ISSN |
logic resource,classical stuck-at fault model,itc benchmarks,sal specification language,configuration memory,fault model,seu un-excitability prover,untestable fault,un-excitability prover,configuration bit,sal model checker,model checking,automatic test pattern generation,multiplexing,testing,field programmable gate arrays | Conference | 1942-9398 |
Citations | PageRank | References |
6 | 0.56 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cinzia Bernardeschi | 1 | 226 | 31.87 |
| Luca Cassano | 2 | 62 | 11.36 |
| Andrea Domenici | 3 | 100 | 17.16 |