Paper Info
Title
Runtime power reduction capability of the IBM POWER7+ chip.
Abstract
Four new energy management features in the POWER7+™ chip enable larger reductions in chip power consumption and further increase energy efficiency of the system during runtime compared with prior POWER7® systems. First, per-core power gating reduces idle power consumption by allowing the system to turn off the voltage to the processor cores when they are not being used. Second, real-time measurement and control of operational guardband allows for higher maximum clock frequency as well as better dynamic voltage selection to reduce power. Third, per-thread utilization counters enable the firmware to sense processor utilization on a finer granularity and set per-core frequency targets with greater accuracy. Finally, a per-core memory access counter allows firmware to more accurately account for power consumption and budget it on a per-processor core basis. These hardware capabilities together enable new EnergyScale™ firmware functions that include voltage optimization to achieve higher turbo frequencies under stressful environmental conditions, automated idle state detection and management, per-core adaptive frequency scaling, and online power modeling for real-time estimation of energy savings.
Year
DOI
Venue
2013
10.1147/JRD.2013.2279598
IBM Journal of Research and Development
Keywords
DocType
Volume
ibm power7,power consumption,dynamic voltage selection,per-core power gating,energy saving,runtime power reduction capability,per-core frequency target,per-core adaptive frequency scaling,per-core memory access counter,chip power consumption,idle power consumption,online power modeling
Journal
57
Issue
ISSN
Citations 
6
0018-8646
2
PageRank 
References 
Authors
0.39
6
10
Name
Order
Citations
PageRank
M. S. Floyd19413.69
Alan J. Drake2707.26
N. S. Schwartz3131.52
R. W. Berry420.39
Charles R. Lefurgy519613.79
Malcolm Ware638927.47
K. Rajamani732434.13
V. Zyuban812212.08
R. Willaman920.39
R. M. Zgabay1020.39