Paper Info
Title
Characterizing the impact of using spare-cores on application performance
Abstract
Increased parallelism on a single processor is driving improvements in peak-performance at both the node and system levels. However achievable performance, in particular from production scientific applications, is not always directly proportional to the core count. Performance is often limited by constraints in the memory hierarchy and also by a node inter-connectivity. Even on state-of-the-art processors, containing between four and eight cores, many applications cannot take full advantage of the compute-performance of all cores. This trend is expected to increase on future processors as the core count per processor increases. In this work we characterize the use of spare-cores, cores that do not provide any improvements in application performance, on current multi-core processors. By using a pulse-width modulation method, we examine the possible performance profile of using a spare-core and quantify under what situations its use will not impact application performance. We show that, for current AMD and Intel multi-core processors, sparecores can be used for substantial computational tasks but can impact application performance when using shared caches or when significantly accessing main memory.
Year
DOI
Venue
2010
10.1007/978-3-642-15277-1_8
Euro-Par (1)
Keywords
Field
DocType
impact application performance,achievable performance,intel multi-core processor,future processor,core count,current multi-core processor,current amd,application performance,production scientific application,possible performance profile,multi core processor
Spare part,Memory hierarchy,Computer science,Parallel computing,Distributed memory,Pulse-width modulation,Modulation,Multi-core processor
Conference
Volume
ISSN
ISBN
6271
0302-9743
3-642-15276-7
Citations 
PageRank 
References 
6
0.50
6
Authors
3
Name
Order
Citations
PageRank
José Carlos Sancho138229.97
Darren J. Kerbyson21102104.36
Michael Lang326619.91