Name
Abstract | ||
|---|---|---|
This paper describes the architecture and principles of operation of sigma-delta ( ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications. In particular, we describe multi-bit ΣΔ TDC architectures; they offer good accuracy with short testing time. However, mismatches among delay cells in delay lines degrade their linearity. Here we propose two methods to improve the overall TDC linearity: a data-weighted-average (DWA) algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our Matlab simulation results demonstrate the effectiveness of these approaches. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1007/s10836-013-5408-6 | J. Electronic Testing |
Keywords | Field | DocType |
Time-to-digital converter,Time measurement,Sigma-delta modulation,Multi-bit,Calibration,High-speed I/O interface circuit testing | Ring oscillator,Computer science,Linearity,Converters,Delta-sigma modulation,Electronic engineering,Real-time computing,Sigma delta modulation,Time-to-digital converter,Calibration,Matlab simulation | Journal |
Volume | Issue | ISSN |
29 | 6 | 0923-8174 |
Citations | PageRank | References |
1 | 0.38 | 5 |
Authors | ||
13 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Satoshi Uemori | 1 | 10 | 3.24 |
| Masamichi Ishii | 2 | 1 | 0.38 |
| Haruo Kobayashi | 3 | 38 | 25.15 |
| Daiki Hirabayashi | 4 | 3 | 1.47 |
| Yuta Arakawa | 5 | 1 | 0.38 |
| Yuta Doi | 6 | 1 | 1.06 |
| Osamu Kobayashi | 7 | 18 | 4.56 |
| Tatsuji Matsuura | 8 | 27 | 8.16 |
| Kiichi Niitsu | 9 | 126 | 38.14 |
| Yuji Yano | 10 | 30 | 5.17 |
| Tatsuhiro Gake | 11 | 1 | 0.38 |
| Takahiro J. Yamaguchi | 12 | 176 | 35.24 |
| Nobukazu Takai | 13 | 30 | 11.68 |