Name
Abstract | ||
|---|---|---|
From the viewpoint of a low-power pipeline ADC design, a comparison between two conventional power reduction techniques is discussed. The comparison shows that the amplifier sharing technique has an advantage in terms of the power reduction effect. To confirm the advantage, a test chip of 10-bit 80-MSPS ADC using the amplifier sharing technique is fabricated. The test chip dissipates 55 mW at 80 MSPS (Mega Sample Per Second). |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietfec/e89-a.7.2003 | IEICE Transactions |
Keywords | Field | DocType |
conventional power reduction technique,low-power design,low-power pipeline,10-bit 80-msps pipeline adcs,power reduction effect,test chip,mega sample,adc design,10-bit 80-msps adc,amplifier sharing technique,pipeline | Flight dynamics (spacecraft),Chip,Theoretical computer science,Analog-to-digital converter,Electronic engineering,Mathematics,Amplifier,Embedded system | Journal |
Volume | Issue | ISSN |
E89-A | 7 | 0916-8508 |
Citations | PageRank | References |
2 | 0.55 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomohiko Ito | 1 | 16 | 4.40 |
| Daisuke Kurose | 2 | 17 | 5.11 |
| Takeshi Ueno | 3 | 20 | 4.27 |
| Takafumi Yamaji | 4 | 55 | 18.00 |
| Tetsuro Itakura | 5 | 187 | 33.44 |