Paper Info
Title
Efficient mapping and acceleration of AES on custom multi-core architectures
Abstract
Multi-core processors can deliver significant performance benefits for multi-threaded software by adding processing power with minimal latency, given the proximity of the processors. Cryptographic applications are inherently complex and involve large computations. Most cryptographic operations can be translated into logical operations, shift operations, and table look-ups. In this paper we design a novel processor (called mu-core) with a reconfigurable Arithmetic Logic Unit, and design custom two-dimensional multi-core architectures on top of it to accelerate cryptographic kernels. We propose an efficient mapping of instructions from the multi-core grid to the individual processor cores and illustrate the performance of AES-128E algorithm over custom-sized grids. The model was developed using Simulink and the performance analysis suggests a positive trend towards development of large multi-core (or multi- µ-core) architectures to achieve high throughputs in cryptographic operations. Copyright © 2010 John Wiley & Sons, Ltd.
Year
DOI
Venue
2011
10.1002/cpe.1647
Concurrency and Computation: Practice and Experience
Keywords
DocType
Volume
significant performance benefit,performance analysis,cryptographic operation,design custom two-dimensional multi-core,Multi-core processor,cryptographic kernel,custom multi-core architecture,individual processor core,multi-core grid,large multi-core,efficient mapping,large computation
Journal
23
Issue
ISSN
Citations 
4
1532-0626
0
PageRank 
References 
Authors
0.34
8
2
Name
Order
Citations
PageRank
Amit Pande126924.58
Joseph Zambreno237744.73