Name
Title | ||
|---|---|---|
A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25-<tex>$muhbox m$</tex>CMOS |
Abstract | ||
|---|---|---|
This paper presents an adaptive finite impulse response (FIR) equalizer with continuous-time wide-bandwidth delay line in CMOS 0.25-mum process for 2.5-Gb/s to 3.5-Gb/s data communications. To achieve wide bandwidth, fractionally spaced structure is used and an inverter with active-inductor load design is proposed as the delay cell of the tap delay line. Close loop adaptation of the fractionally s... |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/JSSC.2006.875302 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Finite impulse response filter,Delay lines,Detectors,Adaptive equalizers,Frequency,CMOS process,Data communication,Bandwidth,Inverters,Data mining | Journal | 41 |
Issue | ISSN | Citations |
8 | 0018-9200 | 14 |
PageRank | References | Authors |
1.15 | 13 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| xiaofeng lin | 1 | 17 | 1.91 |
| Jin Liu | 2 | 104 | 17.01 |
| Hoi Lee | 3 | 513 | 69.98 |
| hao liu | 4 | 14 | 1.15 |