Name
Abstract | ||
|---|---|---|
Fast reconfiguration is a mandatory feature for reconfigurable computing architectures. Research in this area has been increasingly focusing on new reconfiguration techniques that can sustain the architecture performance and to allow the simultaneous execution, at the same stage, of configuration and computation tasks. In this context, this paper presents a new dynamic reconfiguration technique, based on a configuration cache, that tackles this challenge by configuring and executing operations on functional units during the execution stage. This approach is implemented in a pipelined reconfigurable multiple-issue architecture called 2D-VLIW. Our dynamic reconfiguration technique takes advantage of the 2D-VLIW pipelined execution by starting reconfiguration concurrently to activities like reading operand registers and executing operations. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/IPDPS.2006.1639485 | IPDPS |
Keywords | Field | DocType |
new dynamic reconfiguration technique,execution stage,fast reconfiguration,simultaneous execution,dynamic reconfiguration technique,configuration cache,architecture performance,pipelined execution,reconfiguration concurrently,new reconfiguration technique,signal processing,registers,functional unit,computer architecture,pattern recognition,vliw,hardware | Computer architecture,Architecture,Computer science,Cache,Very long instruction word,Parallel computing,Operand,Control reconfiguration,Computation | Conference |
ISBN | Citations | PageRank |
1-4244-0054-6 | 4 | 0.49 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ricardo Santos | 1 | 4 | 0.49 |
| Rodolfo Azevedo | 2 | 271 | 30.84 |
| Guido Araujo | 3 | 40 | 5.23 |