Title
A design-for-test structure for optimising analogue and mixed signal IC test
Abstract
A new Design-for-Test (DfT) structure based on a configurable operational amplifier, referred to as a “swap amp” is presented that allows access to embedded analogue blocks. The structure has minimal impact on circuit performance and has been evaluated on a custom designed Phase Locked Loop (PLL) structure. A test chip containing faulty and fault free versions of this PLL structure, with and without DfT modifications, has been fabricated and an evaluation of this DfT scheme based on the swap-amp structure carried out. It is shown that for embedded analogue blocks, the DfT strategy can not only improve and simplify analogue and mixed signal IC test, but can also be used for diagnostics
Year
DOI
Venue
1995
10.1109/EDTC.1995.470424
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Keywords
Field
DocType
design-for-test structure,test chip,configurable operational amplifier,mixed analogue-digital integrated circuits,dft modification,pll structure,mixed signal ic test,swap-amp structure,dft modifications,design for testability,circuit performance,embedded analogue block,dft strategy,custom designed phase locked loop,integrated circuit testing,operational amplifiers,swap amp,dft scheme,phase locked loops,optimising analogue,diagnostics,embedded analogue blocks,phase lock loop,switches,design optimization,chip,design for test,operational amplifier,integrated circuit
Design for testing,Phase-locked loop,And mixed signal,Computer science,Fault free,Real-time computing,Chip,Electronic engineering,Circuit performance,Operational amplifier,Built-in self-test
Conference
ISSN
ISBN
Citations 
1066-1409
0-8186-7039-8
11
PageRank 
References 
Authors
1.25
8
4
Name
Order
Citations
PageRank
A. H. Bratt1182.80
A. M. D. Richardson2111.59
R. J. A. Harvey3374.10
A. P. Dorey4335.37