Name
Title | ||
|---|---|---|
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor |
Abstract | ||
|---|---|---|
A high-speed, low-power and compact processing element (PE) using quaternary differential logic is proposed for a multi-core single-instruction multiple-data (SIMD) processor. A two-bit addition which is the critical path of the ALU is attributed to a one-digit quaternary addition that is directly performed by using multiple-valued current- mode (MVCM) differential logic circuitry. A one-digit quaternary flip-flop is also simply implemented by using the MVCM differential logic circuitry. The efficiency of the proposed quaternary PE is demonstrated using 0.18 mum CMOS HSPICE simulation in comparison with a corresponding CMOS implementation. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISMVL.2007.14 | ISMVL |
Keywords | Field | DocType |
compact processing element,m cmos hspice simulation,mvcm differential logic circuitry,two-bit addition,quaternary differential logic,one-digit quaternary addition,processing element,corresponding cmos implementation,differential logic circuitry,one-digit quaternary flip-flop,multi-core simd processor,proposed quaternary,parallel processing,adders,logic design,single instruction multiple data,process design,very large scale integration,critical path,energy efficiency,logic circuits,power dissipation | Logic synthesis,Computer science,Logic circuitry,Parallel computing,SIMD,CMOS,Electronic engineering,Processing element,Critical path method,Multi-core processor,Simd processor | Conference |
ISSN | ISBN | Citations |
0195-623X | 0-7695-2831-7 | 7 |
PageRank | References | Authors |
0.74 | 7 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hirokatsu Shirahama | 1 | 28 | 5.25 |
| Akira Mochizuki | 2 | 61 | 9.26 |
| Takahiro Hanyu | 3 | 441 | 78.58 |
| Masami Nakajima | 4 | 61 | 12.45 |
| Kazutami Arimoto | 5 | 95 | 29.82 |