Name
Abstract | ||
|---|---|---|
This paper present a low-power 10-GHz divide-by-3/4 prescaler for 60-GHz high data rate short range wireless communication systems. Design techniques utilized to optimize the power consumption are addressed. The critical circuit, current-mode-logic (CML) blocks, are optimized to achieve high speed and low power consumption simultaneously. The prescaler is implemented in a low-cost commercial 0.18-μm SiGe BiCMOS technology. The maximum operating frequency is up to 10 GHz, with 8.6 mW power consumption in 1.8 V supply. The core area is 190 μm×120 μm. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/APCCAS.2012.6419020 | APCCAS |
Keywords | Field | DocType |
short range wireless communication,low-power divide-by-3/4 prescaler,low power consumption,sige bicmos technology,sige,current-mode logic,current-mode-logic blocks,frequency 10 ghz,low-power electronics,bicmos integrated circuits,voltage 1.8 v,bipolar mimic,prescalers,size 0.18 mum,bipolar mmic,frequency 60 ghz,critical circuit,ge-si alloys,power 8.6 mw,low-power high-speed dual-modulus prescaler,gb/s applications,low power electronics | Frequency divider,Operating frequency,Dual-modulus prescaler,Computer science,Bicmos technology,Electronic engineering,Data rate,Current-mode logic,Electrical engineering,Low-power electronics,Power consumption | Conference |
ISBN | Citations | PageRank |
978-1-4577-1728-4 | 1 | 0.43 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keping Wang | 1 | 8 | 4.42 |
| Kaixue Ma | 2 | 38 | 19.01 |
| Kiat Seng Yeo | 3 | 365 | 63.72 |