Name
Abstract | ||
|---|---|---|
In this paper, a hardware implementation of Support Vector Machine (SVM) classifier for acceleration has been proposed based on pipelined adder, in which the speedups outperform other existing architectures. The adder whose critical path has been efficiently shortened by pipeline technology, constituted the main arithmetic elements in SVM processing. Therefore, a higher processing frequency and throughput have been achieved. Synthesize results in Design Compiler have shown that the operating frequency of the parallel processing elements can reach to 1.16GHz. 1.44X and 1.21X speedups are gained compared with implementations using RCA and KS adder with little area overhead and 3.5X GMACs improvement than other existing architectures on FPGA is obtained. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/DICTAP.2014.6821648 | DICTAP |
Keywords | Field | DocType |
adders,hardware acceleration,arithmetic elements,hardware implementation,pattern classification,parallel architectures,svm processing,svm classifier,support vector machine classifier,pipeline arithmetic,gmac,hardware accerleration,design compiler,pipeline technology,support vector machines,pipelined adder,acceleration,kernel,hardware,computer architecture | Kernel (linear algebra),Adder,Computer science,Support vector machine,Parallel computing,Field-programmable gate array,Compiler,Carry-save adder,Hardware acceleration,Critical path method | Conference |
ISSN | Citations | PageRank |
2377-858X | 1 | 0.36 |
References | Authors | |
9 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chang Liu | 1 | 15 | 7.17 |
| Fei Qiao | 2 | 94 | 35.38 |
| Xinghua Yang | 3 | 9 | 4.00 |
| Huazhong Yang | 4 | 2239 | 214.90 |