Name
Abstract | ||
|---|---|---|
This paper proposes Multiplexer-Flip-Flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose Multiplexer-Latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis shows that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to the traditional pipeline topology. To verify the function of the proposed design, a chips is implemented with the proposed 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the proposed serializer with MUX-FFs are bit-error-free (with BER <; 10-12), operating at up to 12 Gbit/s. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISCAS.2012.6271795 | ISCAS |
Keywords | Field | DocType |
combinational circuits,mux-ff,multiplexing,pipeline,mux-latch,serial link transmitter,cmos technology,multiplexer flip-flops,cmos logic circuits,low gate count serializer topology,size 90 nm,cascaded latches,flip-flops,low gate-count,pipeline topology,serial link,multiplexer latch,logic function,pipeline processing,logic gates,pipelines,topology | Topology,Logic gate,Gate count,Sequential logic,Computer science,Serializer,Combinational logic,Electronic engineering,CMOS,Multiplexer,Multiplexing | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4673-0218-0 | 2 |
PageRank | References | Authors |
0.42 | 7 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei-Yu Tsai | 1 | 73 | 5.06 |
| Ching-Te Chiu | 2 | 304 | 38.60 |
| Jen-Ming Wu | 3 | 62 | 19.81 |
| Shawn S. H. Hsu | 4 | 29 | 7.01 |
| Yarsun Hsu | 5 | 199 | 39.62 |
| Ying-Fang Tsao | 6 | 6 | 0.90 |