Name
Abstract | ||
|---|---|---|
In this paper, we propose an efficient design and implementation results of a high speed 2TX-2RX multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor includes bit-parallel processing transmitter physical layer convergence procedure (TX-PLCP) processor and space-division multiplexing (SDM) symbol detector, which have been optimized for low power consumption and low hardware overhead. It was implemented using 0.18-mum CMOS technology. The proposed architecture can operate at a 40-MHz clock frequency and supports the maximum data rate of 130 Mbps. The logic gate count for the processor is 978 K and the power consumption is 62/284 mW (TX / RX), respectively. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISCAS.2009.5117820 | ISCAS |
Keywords | Field | DocType |
low-power baseband processor,low power consumption,microprocessor chips,power 284 mw,ofdm modulation,frequency 40 mhz,low-power electronics,cmos technology,size 0.18 mum,mimo communication,cmos logic circuits,multiple-input multiple-output orthogonal frequency division multiplexing system,power 62 mw,wireless lan,mimo-ofdm system,hardware,parallel processing,logic gate,transmitters,ofdm,low power electronics,mimo,detectors,logic gates,baseband,physical layer | MIMO-OFDM,Baseband,Computer science,MIMO,Electronic engineering,Baseband processor,Multiplexing,Clock rate,Orthogonal frequency-division multiplexing,Low-power electronics | Conference |
ISBN | Citations | PageRank |
978-1-4244-3828-0 | 4 | 0.59 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Junha Im | 1 | 10 | 1.83 |
| Misuk Cho | 2 | 9 | 1.14 |
| Yunho Jung | 3 | 136 | 24.95 |
| Jaeseok Kim | 4 | 405 | 58.33 |