Name
Abstract | ||
|---|---|---|
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIMM channels at the first-level connecting the memory controller and advanced memory buffers (AMBs); and DDR2 buses at the second-level connecting the AMBs with DRAM chips. We propose an AMB prefetching method that prefetches memory blocks from DRAM chips to AMBs. It utilizes the redundant bandwidth between the DRAM chips and AMBs but does not consume the crucial channel bandwidth. The proposed method fetches K memory blocks of L2 cache block sizes around the demanded block, where K is a small value ranging from two to eight. The method may also reduce the DRAM power consumption by merging some DRAM precharges and activations. Our cycle-accurate simulation shows that the average performance improvement is 16% for single-core and multi-core workloads constructed from memory-intensive SPEC2000 programs with software cache prefetching enabled; and no workload has negative speedup. We have found that the performance gain comes from the reduction of idle memory latency and the improvement of channel bandwidth utilization. We have also found that there is only a small overlap between the performance gains from the AMB prefetching and the software cache prefetching. The average of estimated power saving is 15% |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISPASS.2007.363740 | ISPASS |
Keywords | Field | DocType |
dynamic random access memory,interconnect structure,dual in-line memory module,power saving,storage management,fully-buffered dimm,dram-level prefetching,channel bandwidth utilization,memory controller,spec2000 program,multicore processor,l2 cache block,dram chips,redundant bandwidth,memory block,storage management chips,dram power consumption,software cache prefetching,idle memory latency,dram chip,memory latency,software performance,multicore processing,process design,chip,bandwidth,merging | Dram,Dynamic random-access memory,Fully Buffered DIMM,Computer science,CPU cache,Parallel computing,Real-time computing,Computer hardware,Memory rank,Memory controller,CAS latency,Speedup | Conference |
ISBN | Citations | PageRank |
1-4244-1082-7 | 9 | 0.86 |
References | Authors | |
16 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiang Lin | 1 | 403 | 19.41 |
| Hongzhong Zheng | 2 | 235 | 11.39 |
| Zhichun Zhu | 3 | 514 | 31.77 |
| Zhao Zhang | 4 | 163 | 7.97 |
| Howard David | 5 | 399 | 12.83 |