Name
Title | ||
|---|---|---|
Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme |
Abstract | ||
|---|---|---|
Emerging devices open the way to build nanoscale logic cells, dedicated to high-density reconfigurable computation. Nevertheless, in an architectural context, fine-grain logic cells integration is limited by traditional interconnection scheme and associated overload. This paper describes an interconnection scheme, based on static and incomplete interconnection topologies. We also propose a method to map functions onto such architectures. Then, to evaluate 4 proposed topologies, we test mapping efficiency and fault tolerance. The analyses show that this approach could improve scalability of traditional FPGAs by a factor of 8. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ICECS.2009.5410800 | Yasmine Hammamet |
Keywords | Field | DocType |
fault tolerance,field programmable gate arrays,logic circuits,nanoelectronics,network topology,FPGAs,associated overload,fault tolerance,fine-grain logic cells integration,high-density reconfigurable computation,inter-stage fixed interconnection scheme,interconnection topologies,mapping efficiency,nanoscale devices,nanoscale logic cells,reconfigurable cell matrices,scalability | Nanoelectronics,Logic gate,Computer science,Field-programmable gate array,Electronic engineering,Network topology,Fault tolerance,Interconnection,Scalability,Computation | Conference |
ISBN | Citations | PageRank |
978-1-4244-5091-6 | 0 | 0.34 |
References | Authors | |
1 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pierre-Emmanuel Gaillardon | 1 | 355 | 55.32 |
| Fabien Clermidy | 2 | 797 | 61.56 |
| Ian O'Connor | 3 | 11 | 3.29 |
| Junchen Liu | 4 | 54 | 6.61 |
| Renaud Daviot | 5 | 2 | 1.06 |