Name
Abstract | ||
|---|---|---|
Power consumption has become a major consideration in nanometer chip design. Since the dynamic power is proportional to V dd2, and the static power is proportional to V dd, lowering power supply voltage is an efficient method to reduce the power usage. In this paper, we adopt the row-based dual-supply voltage (DSV) scheme. DSV assigns a low power supply voltage to timing non-critical gates for the power saving. Contrary to the traditional region-based voltage island works, the row-based approach creates voltage islands along the circuit rows. This kind of fine grid voltage islands give more flexibility on gate voltage assignment such that the low voltage gates can be selected primarily based on timing and design logic, which in turn minimizes the shifter insertion. We present a two-stage flow to generate voltage islands for every two mirrored circuit rows and place gates legally inside each island. To the best of our knowledge, this is also the first work to cover latch and LCB (local clock buffer) handling and shifter placement in voltage island generation. The experimental results demonstrate the effectiveness and efficiency of our approach. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1145/2593069.2593207 | DAC |
Keywords | Field | DocType |
circuit rows,algorithms,design,nanometer chip design,power consumption,shifter insertion,microprocessor chips,power saving,low-power electronics,shifter placement,local clock buffer,placement,gate voltage assignment,clocks,lcb,design aids,integrated circuit design,buffer circuits,row based dual-supply voltage island generation,dual supply voltage,fine grid voltage islands,nanoelectronics,clustering | CPU core voltage,Computer science,Voltage optimisation,Electronic engineering,Dynamic demand,Low voltage,Electrical engineering,Voltage regulator,Switched-mode power supply,Constant power circuit,Voltage divider | Conference |
ISSN | Citations | PageRank |
0738-100X | 1 | 0.35 |
References | Authors | |
18 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hua Xiang | 1 | 219 | 17.82 |
| Haifeng Qian | 2 | 476 | 57.19 |
| Ching Zhou | 3 | 18 | 3.92 |
| Yu-Shiang Lin | 4 | 87 | 13.27 |
| Fanchieh Yee | 5 | 6 | 1.81 |
| Andrew Sullivan | 6 | 3 | 1.45 |
| Pong-Fei Lu | 7 | 65 | 13.85 |