Name
Abstract | ||
|---|---|---|
The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical structure of processing communication and memory name-space management resources to provide a scalableNUMA environment. Ensembles of 8 HP PA-RISC7100 microprocessorsemploy an internal cross-bar switch and directory based cache coherence scheme to provide a tightly coupled SMP.Up to 16 processing ensembles are interconnected by a 4 ring network incorporating a full hardware implementation of the SCI protocol for a full system configuration of 128 processors. This paper presents the findings of a set of empirical studies using both synthetic test codes and full applications for the Earth and space sciences to characterize the performance properties of this new architecture. It is shown that overhead and latencies of global primitive mechanisms, while low in absolute time, are significantly more costly than similar functions local to an individual processor ensemble. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1145/224170.224360 | SC |
Keywords | Field | DocType |
fm messaging primitive,host memory,high performance messaging,illinois fast messages,memory name-space management resource,commercial implementation,new generation,latency andusable bandwidth,cache coherence scheme,network interface,full application,illinois fast message,full hardware implementation,buffer management,network coprocessor,full system configuration,new architecture,one-way latency,low latency andhigh bandwidth,messaging layer,api messaging layer,processing communication,full cache coherence,high performance,input output,measurement,parallel computer,modeling,division of labor,low latency,hardware,shared memory,software performance,software systems,application software,ring network,bandwidth,cache coherence,workstations,empirical study,coprocessors | Computer science,Network packet,Parallel computing,Workstation,Computer network,Bandwidth (signal processing),Latency (engineering),Coprocessor,Virtual Interface Architecture,Myrinet,Operating system,Network interface | Conference |
ISSN | ISBN | Citations |
1063-9535 | 0-89791-816-9 | 250 |
PageRank | References | Authors |
47.70 | 15 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Scott Pakin | 1 | 1098 | 134.55 |
| Mario Lauria | 2 | 628 | 95.12 |
| Andrew A. Chien | 3 | 3696 | 405.97 |