Name
Abstract | ||
|---|---|---|
Latent faults represent a potential obstacle in the synthesis of highly reliable digital computer systems. A simulation of an NMR redundant processor system was constructed using a gate level simulation package. The ability of each digital processor to react to randomly induced stuck-at faults is measured, and the amount of time it took the processor's control program to propagate faults to an output was recorded. These propagation times represent the latency times of the faults. The effect of fault latency in degrading system reliability is explored. |
Year | DOI | Venue |
|---|---|---|
1987 | 10.1109/TC.1987.5009523 | IEEE Trans. Computers |
Keywords | Field | DocType |
reliable computer system,fault latency,digital processor,gate level simulation package,degrading system reliability,induced stuck-at fault,nmr redundant processor system,reliable digital computer system,latent fault,control program,latency time,real time systems,reliability,process control,computer architecture,fault coverage | Stuck-at fault,General protection fault,Fault coverage,Computer science,Latency (engineering),Software fault tolerance,Real-time computing,Control reconfiguration,Fault model,Fault indicator | Journal |
Volume | Issue | ISSN |
36 | 8 | 0018-9340 |
Citations | PageRank | References |
2 | 0.47 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. L. Swern | 1 | 2 | 0.47 |
| S. J. Bavuso | 2 | 2 | 0.47 |
| A. L. Martensen | 3 | 2 | 0.47 |
| P. S. Miner | 4 | 2 | 0.47 |