Paper Info
Title
The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era
Abstract
Increase of the process variability with aggressive technology scaling causes many productivity issues in VLSI manufacturing. Analysis about the relationship between process variability and failure has been performed to specify guidelines in both technology and design aspects for yield optimization. By applying the proposed methodology, the core scheme and the operating voltage of the 200MHz SRAM were determined to secure the immunity to operational failures. In DFM point of view, the statistical circuit analysis for failure characteristics is indispensable to guarantee an optimal yield in manufacturing.
Year
DOI
Venue
2008
10.1109/ISQED.2008.108
ISQED
Keywords
Field
DocType
operational failure,nano-scale era,statistical circuit analysis,yield optimization,failure characteristic,robust sram,aggressive technology scaling,dfm point,statistical failure analysis,optimal yield,vlsi manufacturing,process variability,core scheme,design optimization,dfm,design for manufacture,nanotechnology,statistical analysis,failure analysis,very large scale integration,productivity,voltage,robustness,sram
Computer science,Voltage,Electronic engineering,Static random-access memory,Robustness (computer science),Network analysis,Process variability,Very-large-scale integration,Design for manufacturability,Reliability engineering,Operating voltage
Conference
Citations 
PageRank 
References 
1
0.37
2
Authors
7
Name
Order
Citations
PageRank
Young-Gu Kim141.22
SooHwan Kim2608.05
Hoon Lim310.37
Sanghoon Lee4366.83
Keun-Ho Lee5379.90
Young-Kwan Park6294.67
Moon-Hyun Yoo7123.84