Name
Abstract | ||
|---|---|---|
This paper investigates the performance of passive and active inductors for digital Si-CMOS technologies. The extreme low-resistivity of the Si-substrate and the absence of thick top metal layers in digital-CMOS processes prevent the implementation of high-Q passive inductors, and demand alternate solutions. A detailed comparison between the active and passive inductors based on several performance criteria such as Q-factor, area, tunability, noise, linearity, EMI, floor-planning etc reveals the tremendous potential of the high-Q tunable active inductors. An optimization guideline for the grounded-inductor topology has also been suggested. As a basis of comparison, oscillators have been implemented using both the inductors. The active inductor VCO achieves a much higher tuning range and occupies a much smaller die-area than the passive implementation at the cost of degraded phase-noise performance. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1693443 | 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS |
Keywords | Field | DocType |
active inductor, digital Si-CMOS, EMI, floor-planning, linearity, phase-noise, quality-factor, spiral inductor, tunability, tuning range, VCO | Computer science,Linearity,Phase noise,Inductor,Electronic engineering,Network topology,CMOS,Voltage-controlled oscillator,Electrical engineering,EMI,Topology (electrical circuits) | Conference |
ISSN | Citations | PageRank |
0271-4302 | 2 | 0.96 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. Mukhopadhyay | 1 | 2 | 0.96 |
| S. W. Yoon | 2 | 2 | 0.96 |
| Youngjin Park | 3 | 116 | 20.53 |
| Chang-ho Lee | 4 | 25 | 5.00 |
| S. Nuttinck | 5 | 2 | 0.96 |
| Joy Laskar | 6 | 184 | 31.26 |