Name
Abstract | ||
|---|---|---|
This paper presents hardware architecture to perform the basic arithmetic operation addition using Cellular Automata (CA). This age old problem of addition were previously solved by ripple circuit or carry look ahead circuit or by using a combination of them. Each of these circuits is purely combinational in nature and their complexity is centered on the number of logic gates and the associated gate delays. On the contrary, in our CA based design the complexity is mainly centered on the number of clock cycles required to finish the computation instead of the gate delays. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ICIT.2008.18 | ICIT |
Keywords | Field | DocType |
hardware architecture,clock cycle,basic arithmetic operation addition,logic gate,gate delay,cellular automaton,cellular automata,associated gate delay,age old problem,basic arithmetic operations,ripple circuit,adders,circuit complexity,logic gates,digital circuits,computer aided manufacturing,automata,digital circuit,logic design,testing | Logic synthesis,Cellular automaton,Digital electronics,Logic gate,Adder,Circuit complexity,Computer science,Arithmetic,Cycles per instruction,Hardware architecture | Conference |
Citations | PageRank | References |
10 | 2.74 | 2 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pabitra Pal Choudhury | 1 | 69 | 28.27 |
| Sudhakar Sahoo | 2 | 51 | 13.13 |
| Mithun Chakraborty | 3 | 42 | 12.16 |