Name
Abstract | ||
|---|---|---|
In this paper the additional chip size of a Proportional/Integral/Differential (PID) controller in a multithreaded processor is evaluated. The task of the PID unit is to stabilize a thread's throughput, the instruction per cycle rate (IPC rate). The stabilization of the IPC rate allocated to the main thread increases the efficiency of the processor and also the execution time remaining for other threads. The overhead introduced by the PID controller implementation in the VHDL model of an embedded Java real-time-system is examined. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1007/978-3-642-16256-5_3 | SEUS |
Keywords | Field | DocType |
pid controller implementation,multithreaded processor,main thread,cycle rate,execution time,ipc rate,additional chip size,chip-size evaluation,vhdl model,embedded java real-time-system,pid unit,real time,instructions per cycle,chip,real time systems,pid controller | Instructions per cycle,Embedded Java,Control theory,PID controller,Computer science,Real-time computing,Thread (computing),Chip size,Throughput,VHDL,Embedded system | Conference |
Volume | ISSN | ISBN |
6399 | 0302-9743 | 3-642-16255-X |
Citations | PageRank | References |
0 | 0.34 | 16 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael Bauer | 1 | 0 | 0.34 |
| Mathias Pacher | 2 | 107 | 13.21 |
| Uwe Brinkschulte | 3 | 412 | 52.57 |