Paper Info
Title
Expressiveness Of Verifiable Hierarchical Clock Systems
Abstract
The modelling and analysis of multi-component discrete event systems is a challenging research area. Over 30 years, modelling and simulation research of discrete event system specification (DEVS) has been developed with (1) dense-time, (2) the I/O concept, and (3) hierarchical model construction. Nevertheless, DEVS model verification research began relatively recently considering the whole DEVS research history. In the meantime, over 15 years, the automata theory has been developed to cover the dense-time behaviour verification of discrete event systems. Especially, timed automata (TA) has performed the key role in the field.This paper builds on the research results that have been achieved from both theories of DEVS and TA. Thus contributions of this paper can be seen from each side. From the viewpoint of the DEVS theory, a finite and nondeterministic DEVS has been found as a verifiable class. From the viewpoint of the TA theory, a TA which is modular and hierarchical as well as verifiable, is proposed. To show the results, this paper uses the top down manner in which a general formalism is defined first and then its sub-classes are introduced.
Year
DOI
Venue
2008
10.1080/03081070701794876
INTERNATIONAL JOURNAL OF GENERAL SYSTEMS
Keywords
Field
DocType
general dynamic system, hierarchical I/O clock system, DEVS, timed automata, verification
Automata theory,Nondeterministic algorithm,SP-DEVS,Computer science,Automaton,Theoretical computer science,Verifiable secret sharing,DEVS,Finite & Deterministic Discrete Event System Specification,Hierarchical database model
Journal
Volume
Issue
ISSN
37
4
0308-1079
Citations 
PageRank 
References 
2
0.54
13
Authors
2
Name
Order
Citations
PageRank
Moon Ho Hwang1404.77
B. Zeigler21035188.72