Name
Title | ||
|---|---|---|
Memory-Efficiency and high-speed architectures for forward and inverse DCT with multiplierless operation |
Abstract | ||
|---|---|---|
Two-dimensional discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) have been widely used in many image processing systems. In this paper, efficient architectures with parallel and pipelined structures are proposed to implement 8×8 DCT and IDCT processors. In which, only one bank of SRAM (64 words) and coefficient ROM (6 words) is utilized for saving the memory space. The kernel arithmetic unit, i.e. multiplier, which is demanding in the implementation of DCT and IDCT processors, has been replaced by simple adders and shifters based on the double rotation CORDIC algorithm. The proposed architectures for 2-D DCT and IDCT processors not only simplify hardware but also reduce the power consumption with high performances. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1007/11949534_80 | PSIVT |
Keywords | DocType | Volume |
coefficient rom,inverse discrete cosine,inverse dct,high-speed architecture,efficient architecture,two-dimensional discrete cosine,double rotation cordic algorithm,image processing system,2-d dct,high performance,idct processor,multiplierless operation,proposed architecture,image processing,discrete cosine transform | Conference | 4319 |
ISSN | ISBN | Citations |
0302-9743 | 3-540-68297-X | 1 |
PageRank | References | Authors |
0.37 | 18 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tze-yun Sung | 1 | 49 | 10.67 |
| Mao-Jen Sun | 2 | 1 | 0.37 |
| Yaw-Shih Shieh | 3 | 27 | 3.74 |
| Hsi-Chin Hsin | 4 | 73 | 12.34 |