Name
Abstract | ||
|---|---|---|
Cache memory is a usual architecture component, and has the function of increasing the system’s performance. Cache, however, may be responsible for a large part of energy consumption (about 50%) of microprocessors. Based on this, the paper proposes an automated architecture exploration mechanism based on parameter variation of a cache memory hierarchy and NIOS II processor. Results based on Mibench and XiRisc suite have demonstrated that, on average, with 12.5% of the design space, an energy consumption reduction of about 31% has been achieved, as well as an increase of 11% in the performance of the application. Additionally, it was observed that optimal results were found in 67% of the examined cases. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ReConFig.2009.63 | Quintana Roo |
Keywords | Field | DocType |
large part,cache parameters,design space,cache memory,energy consumption,xirisc suite,usual architecture component,automated architecture exploration mechanism,nios ii processor,cache memory hierarchy,low power rtl exploration,energy consumption reduction,silicon,data mining,embedded systems,field programmable gate arrays,fpga,embedded system,soc,space exploration | Pipeline burst cache,Cache pollution,Cache,Computer science,CPU cache,Parallel computing,Real-time computing,Cache algorithms,Cache coloring,Smart Cache,Energy consumption,Embedded system | Conference |
ISBN | Citations | PageRank |
978-0-7695-3917-1 | 0 | 0.34 |
References | Authors | |
10 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. G. Silva-Filho | 1 | 21 | 3.38 |
| Sidney M. L. Lima | 2 | 15 | 2.25 |
| F. C. L. Cox | 3 | 0 | 0.34 |