Paper Info
Title
REPAIR: A Reliable Partial-Redundancy-Based Router in NoC
Abstract
As scale and integration density of network-on-chip increase sharply, more transistors have been integrated into one chip. This unfortunately leads to more unexpected variations and faults in system. In particular, the transient errors and hardware permanent faults have rapidly become the key constraint for large-scale network design. This increasing tendency highlights the incorporation of fault-tolerant solutions for Network-on-Chip (NoC) architecture. In this paper we propose a Reliable Partial-Redundancy-based router architecture (REPAIR). The proposed scheme merely utilizes an additional buffer and a bus to enhance the connectivity of the data path in router. Meanwhile, REPAIR also employs error control coding (ECC) modules and decision-table-based (DT) control logic to implement an efficient online diagnosis and reconfigurable mechanism respectively. The experimental results show the good ability of REPAIR to tolerate hard faults under a high fault rates. Specifically, the silicon protection factor (SPF) of individual router reaches 16.34 and over 95% packets still can be successfully transferred in 16x16 torus network with 650 faults.
Year
DOI
Venue
2013
10.1109/NAS.2013.28
NAS
Keywords
Field
DocType
error control coding,torus network,data path,additional buffer,reliable partial-redundancy-based router,large-scale network design,individual router,control logic,efficient online diagnosis,router architecture,buffer,noc,network routing,maintenance engineering,routing,decision tables,silicon,network on chip,fault tolerance,bus
Network planning and design,Grid network,Computer science,Network packet,Network on a chip,Computer network,Real-time computing,Chip,Redundancy (engineering),Control logic,Router,Embedded system
Conference
Citations 
PageRank 
References 
4
0.41
7
Authors
3
Name
Order
Citations
PageRank
Lei Xie1248.44
Kui-zhi Mei29715.55
Yuhai Li341.42