Paper Info
Title
Phase-locked loop design with SPO detection and charge pump trimming for reference spur suppression
Abstract
As an important factor for long-term jitter in clock synthesis and distribution, reference spurs result from circuit mismatch and nonlinear effects that induce periodic perturbations in phase-locked loops (PLLs). In this paper, a PLL with built-in static phase offset (SPO) detector and charge pump current trimming for self-calibration circuits is proposed. By adjusting the charge pump current ratio determined by an SPO detector, minimum and maximum improvements of 12dB and 22.99dB in reference spur suppression can be achieved. The best improvement reduces the integrated jitter by 10% over a 10kHz to 10MHz bandwidth. The technique is demonstrated for a PLL output frequency from 400 MHz to 1 GHz. The ring oscillator based PLL is designed with 200 KHz bandwidth and 70 degree phase margin. Measurement results from chips across different corners are provided to verify the calibration technique.
Year
DOI
Venue
2014
10.1109/VTS.2014.6818785
VTS
Keywords
Field
DocType
clock distribution,long-term jitter,spo,reference spur,phase locked loop design,reference spur suppression,charge pump current trimming,charge pump trimming,current mismtach,charge pump circuits,built-in static phase offset detector,clock synthesis,frequency synthesizer,charge pump,pll,self-calibration circuits,clocks,bist,phase locked loops,circuit mismatch,spo detection,ring oscillator,phase detectors,nonlinear effect,frequency 400 mhz to 1 ghz,long term jitter,jitter,calibration,detectors
Phase-locked loop,Ring oscillator,Computer science,Control theory,Frequency synthesizer,Electronic engineering,Phase margin,Jitter,Charge pump,Detector,Phase frequency detector
Conference
ISSN
Citations 
PageRank 
1093-0167
0
0.34
References 
Authors
0
6
Name
Order
Citations
PageRank
Sen-wen Hsiao1234.54
Chung-Chun Chen210.82
Randy Caplan300.34
Jeff Galloway431.08
Blake Gray500.68
Abhijit Chatterjee61949269.99